Title: Information Flow Security in Systems With Two Processors. 

Abstract

Multicore processors are the current standard in desktop devices and are
becoming increasingly popular in mobile devices.  Such systems differ from
single processor systems in the memory model to optimise the performance. The
so called relaxed or weak memory models allow processors to see operations of
other processors in a different order. Therefore further program executions
become possible. Current security properties like strong security are based on
semantics of single processor systems and rely on sequential consistent memory
models.  This talk is an introduction to weak memory models and their effects
on security. It further presents semantics for an imperative toy language based
on a dual processor system and a new security property with corresponding type
system.